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IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD
* 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * VCC = 2.5V 0.2V * CMOS power levels (0.4 W typ. static) * Rail-to-Rail output swing for increased noise margin * Available in 96-ball LFBGA package
IDT74ALVCH32374
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
* High Output Drivers: 24mA * Suitable for Heavy Loads
This 32-bit edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology. This high-speed, low-power register is ideal for use as a buffer register for data synchronization and storage. The Output Enable (OE) and clock (CLK) controls are organized to operate the device as four 8-bit registers, two 16-bit registers, or one 32-bit register with common clock. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The ALVCH32374 has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH32374 has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistor.
APPLICATIONS:
* 3.3V high speed systems * 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1OE
A3
3OE
J3
A4
1CLK
A5
3CLK
J4
1D1
D C
A2
3D1
J5
D C
J2
1Q1
3Q1
TO SEVEN OTHER CHANNELS
H3
TO SEVEN OTHER CHANNELS
2OE
4OE
T3
H4
2CLK
E5
4CLK
T4
2D1
D
E2
4D1
N5
D C
N2
C
2Q1
4Q1
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
TO SEVEN OTHER CHANNELS
INDUSTRIAL TEMPERATURE RANGE
1
(c)2000 Integrated Device Technology, Inc.
FEBRUARY 2000
DSC-4909/1
IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
6
1D2
1D4
1D6
1D8
2D2
2D4
2D6
2D7
3D2
3D4
3D6
3D8
4D2
4D4
4D6
4D7
5
1D1
1D3
1D5
1D7
2D1
2D3
2D5
2D8
3D1
3D3
3D5
3D7
4D1
4D3
4D5
4D8
4 1CLK
GND GND
VCC VCC
GND GND
GND GND
VCC VCC
GND
2CLK
3CLK
GND GND
VCC VCC
GND GND
GND GND
VCC VCC
GND
4CLK
3 1OE
GND
2OE
3OE
GND
4OE
2
1Q1
1Q3
1Q5
1Q7
2Q1
2Q3
2Q5
2Q8
3Q1
3Q3
3Q5
3Q7
4Q1
4Q3
4Q5
4Q8
1
1Q2 A
1Q4 B
1Q6 C
1Q8 D
2Q2 E
2Q4 F
2Q6 G
2Q7 H
3Q2 J
3Q4 K
3Q6 L
3Q8 M
4Q2 N
4Q4 P
4Q6 R
4Q7 T
LFBGA TOPVIEW
96 BALL LFBGA PACKAGE ATTRIBUTES
1.5mm Max. 1.4mm Nom. 1.3mm Min.
0.8mm
6 5 4 3 2 1 A B C D E F G H J K L M N P R T
TOP VIEW
A 1 2 3
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
5.5mm 4 5 6
13.5mm
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IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TSTG IOUT IIK IOK ICC ISS Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND -0.5 to +4.6 -0.5 to VCC+0.5 -65 to +150 -50 to +50 50 -50 100
Unit V V C mA mA mA mA
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
NOTE: 1. As applicable to the device type.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
PIN DESCRIPTION
Pin Names xDx xCLK xQx xOE Data Inputs
(1)
FUNCTION TABLE (EACH FLIP-FLOP)(1)
Description xOE L L L H Inputs xCLK H or L X xDx H L X X Outputs xQx H L Q(2) Z
Clock Inputs 3-State Outputs 3-State Output Enable Inputs (Active LOW)
NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH Transition 2. Output level of Q before the indicated steady-state conditions were established.
3
IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- -0.7 100 0.1 Max. -- -- 0.7 0.8 5 5 10 10 -1.2 -- 40 V mV A A A A V Unit V
Quiescent Power Supply Current Variation
--
--
750
A
NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. - 75 75 - 45 45 --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- 500
Unit A A A
4
IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OPERATING CHARACTERISTICS, TA = 25C
VCC = 2.5V 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 62 32 VCC = 3.3V 0.3V Typical 60 36 Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V 0.2V Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW tSK(O) Propagation Delay xCLK to xQx Output Enable Time xOE to xQx Output Disable Time xOE to xQx Setup Time, data before CLK Hold Time, data after CLK Pulse Duration, CLK HIGH or LOW Output Skew(2) 2.1 0.6 3.3 -- -- -- -- -- 2.2 0.5 3.3 -- -- -- -- -- 1.9 0.5 3.3 -- -- -- -- 500 ns ns ns ps 1 5.3 -- 4.7 1.2 4.3 ns 1 6.2 -- 5.9 1 4.8 ns Parameter Min. 150 1 Max. -- 5.3 VCC = 2.7V Min. 150 -- Max. -- 4.9 VCC = 3.3V 0.3V Min. 150 1 Max. -- 4.2 Unit MHz ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2 Skew between any two outputs of the same package and switching in the same direction.
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IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50 6 2.7 1.5 300 300 50 VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
ALVC Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE
VCC 500 Pulse Generator
(1, 2)
VLOAD Open GND
VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
ALVC Link
VIN D.U.T. RT
VOUT
500 CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
ALVC Link
INPUT
tPLH1
tPHL1
VIH VT 0V VOH VT VOL VOH VT VOL
Set-up, Hold, and Release Times
OUTPUT 1
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
VT
tSK (x)
tSK (x)
OUTPUT 2 tPLH2 tPHL2
VT
ALVC Link
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
ALVC Link
Pulse Width
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT ALVC X XX Bus-Hold Temp. Range XX Family XX XXXX Device Type Package
BF 374 32 H 74
Low-Profile Fine Pitch Ball Grid Array 32-Bit Edge Triggered D-Type Flip-Flop with 3-State Outputs 32-Bit Bus Density, 24mA Bus-Hold -40C to +85C
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
7

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